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Re: ADV7181C : How to a fine adjustment the Vsync output timing (SDP)

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The ADV7181C only has the sync timing controls as defined in the manual section 8.15.  All adjustments are based on LLC1 clock and since counter are 11 bits, you should be able to adjust the timing for the 5.6us

 

HS edges can be moved as shown in Figure 51

 

VS is controlled by the 5 bit registers NVBEGIN and NVEND.  These are line count based.  Since for NTSC, one line is 63.556 us, you can't move VS by 5.6us


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