Re: Need help with the power supply for AD7634
Mikhail,I just stumbled onto your ADIsimPower Excel issue comment.We may have fixed the issue already but in some instances the language setting of your operating system (not Excel) affects how Excel...
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Re: AD9822 noise
In addition to Harry's comments, you should also try adjusting the phase of the ADCCLK signal to see if the noise is reduced. The CDSCLK/ADCLK waveform quality is also important- you don't want to see...
View ArticleTx performance at high freq
Using 9361 at 3.6 GHz.The datasheet lists max power at +7 dbm. Uncertain if Linear or Psat. See mask plots as function of gain, but found only at 800 MHz.On our board or ADI Eval board, (single-tone)...
View ArticleLatch a zero for a set period of time?
Desired block:As long as input is nonzero, output should be 1.When input is 0, even for 1 sample, output changes to 0 and stays at zero for n samples. Even if input becomes nonzero again, the output...
View ArticleRe: ADV7180 2xOversampling and LLC
Thank you for your kindly reply.I understood that sampling rate of ADC is 27.0MHz (not 28.636MHz).Now I set YSFM[4:0] is b10011.Can I disable Y Shaping Filter?I would like check difference of Y Shaping...
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Phase noise of ADL5380
I'm interested in what the phase noise of the ADL5380-EVALZ is across it's range of operating frequencies, in the new configuration with balun which spans the whole range from 400-6000 MHz. Is there...
View ArticleRe: Channel Bandwidth on FMCOMMS2
On a separate note,may I ask what determines the maximum possible bandwidth of FMCOMMS2 to 56MHz? The baseband PLL synthesizer could be programmed to 1400MHz, so what limits FMCOMMS2 channel bandwidth...
View ArticleRe: AD9523-1 jitter and phase lock
The spectrum analyzer screenshot is feeding from AD9548 OUT1P SMB connector to a N9030A PXA Signal Analyzer. No, AD9548 out1N SMB connector is open, not terminated with 50 ohm.
View ArticleRe: ADXL... accelerometers : 0g drift equal or different between X and Y ?
Hello Venkat,First of all thank you for your replies to my 3 discussions of today. The sensor IC will not have its plane horizontal with the earth in the normal use of my application (as if putted flat...
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Re: Setting LO frequency taking 40-60ms with libiio
We're using a Xilinx ZC702 development board. If you could also give us some clue how to use the preview files, it would also be appreciated. Thanks, Tom
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Connecting AD8370 VGA to AD9246 A2D in DC coupled mode
Hello,I'm trying to find how to conenct the AD8370 Variable Gain Amp to the AD9246 A2D working at 2Vptp mode.The connection should be DC coupled. THey got diffewrent common mode voltage levels so this...
View ArticleRe: AD9739A-FMC-EBZ rev C vs. rev B changes
The Rev C replaces a jumper header (on rev B) with a toggle switch for ease of changing from the ADF4350 on-board clock to external clock source for the DACCLK. When making the change, the user still...
View ArticleRe: ADL5801
Hi, Ahmet, Would you please clarify the following so that we may better understand what you're trying to do and what the issue is: -- When you say worse result, what aspect is worse, and what are...
View ArticleRe: AD9915 Synchronization
Random phase jumps of the SYNC_CLK (when synchronizing multiple devices) is a sign of metastability of the internal timing between SYNC_IN and REF CLK. Note, as the SYNC_IN continues to run (even after...
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Re: ADL5801
Hi BenjaminI downloaded s parameter of ADL 5801 RF Port and tried to match to 50 ohm with using lossless matching tuner. According to s parameter data I didnt get -0.7 dB return loss value. Yes I try...
View ArticleRe: M25P16 SPI Flash Blackfin Driver
Hardware-controlled chip-select is likely the problem. The response for the READ ID command is 20 bytes long, so you'd need to issue 21 transfer bytes (the first being the command 0x9F, followed by 20...
View ArticleADV7401 INT signal
Is the INT_L signal that is driven out from the ADV7401 synchronous with the output clock, LLC1? How do you select which registers result in the interrupt signal being toggled?
View ArticleRe: ADV7401 INT signal
It is not defined if INT is synchronous with the output clock. It generally doesn't matter since the processor can normally handles edges or level interrupts. From Table 112,0x40 sets up the basic...
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