AD9361
Hi,I want to use the AD9361 and a FPGA for a certain application together with the demo suggested by ADI.In order to select the proper FPGA I would like to know if anyone can tell what is the...
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AD9822 noise
HiI am designing an ADC circuit for CCD, I am used ADC9822 and the circuit is exactly same as datasheet.The sampling rate is 1.25MHz and ADC is programmed in single channel and CDS mode. The noise at...
View ArticleRe: ADF4351 PLL programming question
I am using commercial RF transceiver-Ettus Wbx -> Ettus Research - Product DetailHere is the schematic, PLL on pg 3 -> http://files.ettus.com/schematics/wbx/wbx.pdfMy fpga Xylo-em board (pg...
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Re: EVAL-ADAU1701MINIZ: SigmaStudio's EQs control wrong frequencies
Hello Prius, What is the sample rate set to within the SigmaStudio schematic? This is important in order to generate the proper download parameters for the filters. What are your settings for the...
View ArticleRe: AD9361 RX_FRAME and TX_FRAME signals in FDD
Yes, the mode is controlled by FDD External Control Enable bit in register 0x015. You can read more about this mode (FDD Independent Control) in UG-570 pg 28.
View ArticleRe: Building fmcomms2 in Vivado 2014.2
Yes, I did update the core versions in the tcl before building in 2014.2. Ok I have to go with 2013.4. Thanks
View ArticleHow to I implement non-blocking calls for receiving UDP on Blackfin?
Hi, I'm currently working on an application which receives and mixes multiple RTP streams on different multicast addresses. I have several threads running alongside one another and they all...
View ArticleRe: Re: AD9520-1 Eval Board - layout files available?
Hi George,Attached are images of the 4 layers in .pdf form. Let me know if any details that you need are not showing here. The coloring slightly distorted when I saved them as .pdf's.Regards,Kyle
View ArticleRe: dxe works ok but ldr doesn't run
I found the problem; The issue was to do with the fact that i was not properly initialising my SDRAM or properly organising my heap usage. When creating a simple LED Blink application my memory usage...
View ArticleRe: AD9525 reference clock configuration
Hi, REFA: Yes, you want to remove the 50 ohm resistor and leave C111 present.REFB: Yes, you want to remove the ac coupling capacitor and the 50 ohm termination.Regards,Kyle
View ArticleRe: AD9139, DAC latency from input to output
I will look into this and get back to you.
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Re: AD9102 minimum output frequency?
At the max sampling frequency of 180 MSPS, the part can do about 10 Hz accuracy with 24 bits of tuning word. I don't think it will do it.
View ArticleRe: Question regarding HDMI ARC on ADI chips
Hi Rommel, We test ARC on our products up to 48KHz sampling rates, per the HDMI specification. If you are needing a higher sampling rate, please discuss with your ADI sales contact. -Matt
View Articleheap management functions in CCES
Hi, I'm trying to use some of the heap management functions that should be included in stdlib.h however whenever I compile my project in CCES it's unable to find them. Any suggestions as to what I'm...
View ArticleCED1Z issues
HEllo,My customer is trying to use the CED1Z ADC platform but gets the following error: Windows can see the USB device, but I see the error below in Device Manager. ADI Development...
View ArticleRe: AD-FMCJESDADC1-EBZ
Rejeesh -Once you get a license for the jesd how do you proceed - there are 2 verilog files missing in edk as well as the ngc's for both the jesd and the dds.
View ArticleRe: AD-FMCJESDADC1-EBZ
Follow this: AD-FMCOMMS1-EBZ HDL Reference Design [Analog Devices Wiki] You can use the xco files - as it is, or modify them (if you are planning on modifications).
View ArticleRe: AD9361 VDD_INTERFACE
HI tlili, Yes it is there, Since i am using LVDS (2.5V) interface. I am connecting my data lines, control lines 7 SPI to 2.5V bank of FPGA. Is that ok? or am i wrong ?Please give some clarification on...
View ArticleRe: Using a iCoupler gate driver as a solid-state relay
Hello Mark,I really like the idea:It would be VERY interesting if ADI would consider making a packaged SSR using their isoPwr and iCoupler technology. This would provide a nice building block for use...
View ArticleRx Sample Streaming on Zc702 and FMC2
Hello, I was wondering if there is an example project/step that allows user to stream complex baseband samples from ad9361 to DDR memory connected to zynq chip on Zc702 eval platform mated with FMC2...
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