Re: Change PWM Phase between AH and AL or AH and BH in BF506F
Hello，As you say,if I need an asymmetrical PWM ,I must chang some values in every cycle in double-update mode.So if the frequence is 10k, there are 10000 times of interrupt which is unacceptable....
View ArticleRe: ADIS16229 transmission time and power consumption
Hi Mark, Thanks for your reply, one more question,do you know how much transmit/receive time base one ADI whole demo kit? I just need a rough estimation.
View ArticleRe: AD5732 can't let VoutB output
Hi, Cao. It would greatly help me understand your problem if you could provide a schematic diagram. Please include working supply, references, and logic levels. Would you also be able to answer some...
View ArticleRe: ADIS16000/229 Vibration Sensor Kit(has new version software? )
Hi Mark, Thanks! the problem is I can see the ADIS16229 has been connected to Window but the data can't been saw when I plug start. About LED, I remember that LED sometimes blink.
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Re: ADXL375 evaluation board's behavior at ODR=1600Hz,3200Hz
Hi NeilThank you for your support. I agree that it is small difference.However, a strange output makes a doubt to the performance of ADXL375. Could you make sure that ? Look this picture."-2"data were...
View ArticleRe: Minimum drive current for ADM7172 ?
Hi Rob, The ADM7172 does not require a minimum drive current. Line and Load regulation plots in the datasheet show good operation down to 100uA loads and it will still regulate the output well at no...
View ArticleDoes packing many radios in Single Chip quality it as IoT device?
Blackfin DSP have been in the past 15 years and ARM also there little more in terms of number of years. These days, IoT devices does not requires good Display or good GUI. All that it requires is good...
View ArticleAD1974 sample rate setting.
Hi,all. I'm confused the clock signal relation & register setting, MCLK,sample rate,ALRCLK,ABCLK @AD1974. In the datasheet 11page "CLOCK SIGNALS", I found the following description."In 96 kHz...
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Re: AD9520-4 EVM clock distribution problem
Hi Albert, Can you send me your register settings by saving a setup file in the GUI? I will take a look at them and see if anything jumps out. Can you also probe on the output of the balun to make...
View ArticleAD9548 unresponsive after initial powerup
Our custom Zynq board's AD9548 appears unresponsive after initial powerup, with the Linux ad9548 driver reporting "Unrecognized CHIP_ID 0xFF". Resetting the board with our "poweron reset" switch allows...
View ArticleRe: loopback test
Rick: If you want to do that, try things in the following order: - set the loop back - send the buffer to Tx (this buffer repeats) - start reading Rx (read 2x the Tx buffer, since you will not know...
View ArticleRe: NLMS Block for ADAU1452?
Dear John, Thanks for the reply. Attached is my project. If you have time please check if i had made connection mistakes for the NLMS block. Thanks,Dan
View ArticleRe: Synchro/Resolver Converters
Hi Ryan, Thanks for the update, but I would greatly appreciate if you can answer by following questions 1. What is the relationship between reference frequency and tracking rate. How did you arrive at...
View ArticleMax speed ADV7612BSWZ-P, ADV7511KSTZ-P
I found a data sheet for the ADV7612 that lists the max pixel clock at 170MHz, but then in another part of the data sheet it says it supports resolutions up to 1600x1200. I am used to working in the...
View ArticleEVAL-AD7985EDZ FPGA Code
I bought a EVAL-AD7985EDZ board from Mouser, But could not find the directory "Evaluation Board FPGA Code"in the CD, where can I download it? Thanks.
View ArticleADXL345, 3200Hz Data Ready makes ideal time interval?
Hi. I.m trying to get high sampling rate data from ADXL345.So I set configurations as data rate as 3200Hz and receive data ready through INT1. ADXL345 makes interrupt signal well, but when I measure...
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AD7682 Bandwidth VS Conversion Rate
It is read from datasheet that 250KSPS throughput can only be achieved when ADC is working under full bandwidth. Does it mean that if I set the bandwidth register in ADC to 1/4 bandwidth, I can only...
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AD-FMCDAQ2 PLL locking issue??
HiI uploaded this question a while ago but haven't got any response yet.Please have a look at this and I'd really appreciate your help.:I have an AD-FMCDAQ2 Rev. D and a KC705 board.Following the...
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ADAU1761 Distorted Output
Hi All, Using the EVAL-ADAU1761Z, I tried 1761's basic DSP function and turns out that the output is distorted. INPUT : single ended stereo at LAUX and RAUX (but used only RAUX in DSP program...
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