Could ADV7403 support YPBPR/RGB 1080P30 component input?
Hi,We want to use ADV7403 to design a video system with YPbPr/RGB input.Could it support to 1080P30 analog component input? Another question is could ADV7393 support to 1080P30 output? We also want to...
View ArticleRe: Could ADV7403 support YPBPR/RGB 1080P30 component input?
Correct the Another question is could ADV7393 support to 1080P30 output? We also want to develop a product with this encoder. In datasheet, there's some description about standards supported. Does it...
View ArticleADSP-TS101 Booting Option
Dear Analog Devices Team, We are using ADSP-TS101SAB1Z000 in one of our design, We have made strap pin /BMS as "0" so that the system boots from EPROM/Flash immediately after reset. In the ADSP-TS101...
View ArticleRe: ADAV803 problems
Hello Dave The workaround seems to be a good solution but i wish to know if there is a better one. Signal is braking constantly and periodicaly. I am switching it on and off for a longer and longer...
View ArticleAD9467EBZ ref design
Hello, I hope these queries haven't been answered in some other thread (I tried searching for them but couldn't find any).1) The custom peripheral added to the AXI bus in XPS is axi_adc_1c_0. This...
View ArticleRe: Interfacing ADAU1701 with AD1955
Apologies for the bump. Does there need to be a level shifter from the ADAU1701's 3.3V to the AD1955's 5V when using this buffer? Does the supply voltage of the buffer matter here?
View ArticleRe: AD9915 parallel write timing
Thanks for the clarification. Regarding IO_UPDATE and SYNC_CLK: I understand that one can write in parallel mode multiple registers before doing the IO_UPDATE, so the IO_UPDATE timing does not have to...
View ArticleRe: ADAU1761 at non-audio sample rate (i.e. 51200)
Hello, Yes this is permissible. The data sheet allows for a MCLK period as short as 37 nS in 512 x fs mode. This corresponds to MCLK as high as 27 MHz, or a sample rate of 52.7 KHz. Thus,...
View ArticleADV7188
HelloI would like to ask on the above ADV7188 decoder.I think I see on its datasheet (Rev 0 from 2005) a contrediction between Table 9 and Table 101at the definition of INSEL[3:0] Register about values...
View ArticleRe: AD9364 External LO phase noise
Hello again, I measured the phase noise at the Tx output as you suggested, with internal and external Tx LO - in both cases the phase noise was ~-116dBc/Hz at 5-20MHz offsets (the test was done with Tx...
View ArticleAD5560 used for multiple power supplies
Hi, We are design engineers from the company, currently we have one project to adopt AD5560 for the power source design, we have LCD module driving with different power rails, totally we have five...
View ArticleRe: AD5560 used for multiple power supplies
We are developing the test fixture for LCD modules and our mass production will reach more than 30K per year, thanks.
View ArticleRe: AD9361 Reference Design for the Altera Cyclone V SoC Board
Hi Dragos Many thanks for the reply & link.Can you further help with a feq follow-up questions:Is there a document with a picture the setup of the design similar to the one we have of the Xilinx...
View ArticleRe: No filters in the receive path on FMCOMMs1?
Hi, Charly Does I understand it right ? About the position of LPF filter be populated, between the ADL5380 and AD8366, or between the AD8366 and the ADC? What do you think? Thanks. Zhonghua
View ArticleAD8347 mixer loading
Hello I have some questions from my one of my customers in regard to the device:In non-AGC mode, does he need to place a protection device (PIN diode/limiter) on the input to the mixed to prevent...
View ArticleIntermod level wrt to fundamental reduces with lower input to DAC for AD9364
We are testing the AD9364 in Non-OS mode with scaling the input to the DAC.As the input to the DAC reduces, 3rd order intermod with reference to fundamental levels are reducing, where as it is suppose...
View ArticleRe: ADRF6518 Output common mode
What impedance is the ADRF6518 driving? Can you attach your application schematic? Thanks,Joel
View ArticleRe: AD9361 - initialization data for specific LTE FDD bands
Constantin, You can find the no-OS software on the GitHub: no-OS/ad9361/sw at master · analogdevicesinc/no-OS · GitHubEssentially, you have to call just the ad9361_init() to initialize the part. The...
View ArticleRe: ADV212 HIPI mode issue(compressed image doesn't match the original image)
thanks,I have used 32bits host and DMA width,but the result seems all the same,In fact, the contour of the compressed image (j2c fifle) agree with the original image,pixels' values change,The high...
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