Hi Dragos,
Thanks very much for pointing out the update.
We basically aim to implement a double buffer so that we can transfer a second block from PL while we are processing the first block in the PS side. As far as I understand, 2D DMA realizes this idea. Is the DMAC core provided in the updated design capable of sending interrupts in such a scenario in the first and second loops of DMA transfer? What are the parameters we can control for the DMAC core?
Thanks,
Onur