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Re: Data clock from AD9361 FMC card in DDR mode

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DATA_CLK needs to be terminated in 100ohms in LVDS mode (differentially). This will ensure correct signal amplitude. LVDS driver outputs a differential current that relies on a correct termination resistor value (specified by TIA/EIA-644 as 90ohms - 132ohms) to generate the output differential voltage.

 

DATA_CLK has some control bits for increased drive strength and slew control (register 0x03B). Register 0x03C offers LVDS driver amplitude control. Detailed description is available in UG-671.


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