Hi,
We were able to successfully rectify this now without the need for repeated hardware resets. Basically the issue was quite well explained in AN1337. As per AN1337 some of the MIPI CSI-2 receiver's need to see a LP to HS transition on clock lane before they can enter a state where they can succesfully capture MIPI data. as per AN1337 the best way to do this is to manually toggle the CSI power down BIT ( bit 7 of register at address 0x0 in the CSI Map ) .
In our SW flow we were not doing this at the right place hence we were seeing the issue. once we started doing this at the right place in the SW flow the issue got rectified.
Thanks to the author of AN1337
Regards
Jitender