Re: AXI AD9361 DAC DMA HDL

Hi,

If I understand Lars and Adrian correctly, I would be able to hold the DMA output using the fifo_rd_en signal, and the DMA would not drop packets.  I would also need to synchronize my module's output on the dac_data* signals, with the dac_valid* signals, so the ad9361 core can correctly receive all my data.

Thanks for your replies !  I will implement these in my module accordingly.

Regards