What version of things are you running? We can do more than this on the Zed designs - but they have been updated a little more than the fabric only solutions.
If you are running into a bandwidth issue - turn down the sample rate.
If you are running into a number of samples issue - there are some tweaks to the HDL that can be made.
I'm not sure about your last question - it sounds like it's a generic Xilinx tools question - did you check with them?
-Robin