Hi Ricky,
With the AD9913, the SYNC_CLK is equal to the system clock or SYSCLK and is provided as an output if you are using the on-chip PLL to generate the system clock.
If you do not synchronize your I/O_Updates to the SYNC_CLK there will then be an uncertainty of +/-1SYSCLK period of when the registers are actually updated. Our datasheets usually say that the I/O_Update pulse has to be at least 2 SYNC_CLK periods long. With this, even if the pulse is sent asynchronously it will be captured by at least one SYNC_CLK rising edge. Synchronizing to SYNC_CLK is generally only an issue if you are trying to synchronize the DDS to another signal and need maintain and exact phase relationship with it.