Hi,
We have a piece of standard HDL that takes the link data and when you give it the number of lanes and converters will produce the samples in the output vector in the right order. Maybe that is useful.
hdl/ad_ip_jesd204_tpl_adc_deframer.v at dev_ad9694 · analogdevicesinc/hdl · GitHub
For your case you'd also have to change the SAMPLES_PER_FRAME to 2:
- Lars
Hi,
If you channels are separated by 100kHz a better approach might be to sample a wider band and multiple channels at the same time. Then you can digitally demodulate them in the FPGA, switching between channels can than be done instantaneously.
- Lars
Hi!
I'm writing this to ask you all for a recommendation or "a finger pointed in the right direction". We are making measurements using a load cell, with the following parameters:
For the ADC we've settled upon Analog Devices AD7175-8.
For the ADC power supply we've used ADR435ARZ as an Ultralow Noise power supply.
For driving the load cell (and the AFE mentioned below) we've also used the same ADR435ARZ. This was done to ensure that the load cell is driven by a power supply with as little noise as possible.
The main problem right now is designing an AFE (Analog-Front-End), capable of driving the ADC at such high speed and resolution while having a good SNR, CMRR, sensitivity etc.
By now, we have tried the AD8556 which proved to be a big mismatch compared to the ADC performance.
Can you propose a design that would allow us to achieve such performance from a load cell? We would appreciate either a generic schematic (or app-note), or else a recommendation in terms of specific parts.
I had a look on the following document, but none of the designs mentioned cope with the speed and resolution that we are looking for.
http://www.analog.com/media/en/technical-documentation/application-notes/an43f.pdf
Many thanks!
Sorry for the NOOB question but I am picking up work during someone else's vacation.
I am running the ad9102 through the Quick Start LabVIEW ad9102.vi and all is going well.
I want to set the board so it can be triggered remotely.
I believe I have to set the RUN bit in the pat_status register (0x1E) in order to do this.
I can set the PATTERN_RPT bit in the pat_type register (0x1F) either through the GUI or by editing the regval file.
I can't do likewise with the RUN bit either through the GUI or by editing the regval file.
So my question is threefold:
Thanks in advance,
Simon.
I have a question on ADAU1701 - not sure if this is right place... Newbie - sorry.
I have an instrumentation design needs 8xADAU1701 . Is it possible to synchronise the frame rates of these parts exactly - down a level that the I2S ports if outputting are synchronous? Will this just happen if common reset and clock them?
Further question related to sigmastudio sources for the above part. There is schematic object marked "sine tone with phase and gain". It could suit my purposes well but I have to know to what (time point) is the phase relative. There is no reset or ref pin on the gui object in the schematic - just an output. How is this meant to work.? Ideally I would like to sync it to one of the GPIO input pins and reset it.
hope im not too far off base with these Qs
Hi Hiroyuki-san,
The efficiency is a rough estimate based on the standalone isolated DC-DC product, ADuM5000 (ADM2582E/87E isolated DC-DC is similar). From page 9 of the ADuM5000 datasheet:
We can see that efficiency with 3.3V to 3.3V is up to 35% in the typical case. Choosing 33% makes the quick calculations easier.
From the table you posted, the external current available is:
15 mA 54 Ohm load
29 mA 120 Ohm load (i.e. 14 mA extra compared to the 54 Ohm case)
46 mA No load (i.e. 31 mA extra compared to the 54 Ohm case)
This is why I mentioned an additional 14 mA and 31 mA when there isn't 54 Ohms on the bus.
Regards,
Conal
Hello there,
I am little confused about choosing the best option for balanced output stage from the ADAU1701 DSP.
I was thinking about 2 options, attached all of the them.
I would appreciate help from anyone who can advice witch method to choose, and best one to achieve the BALANCED output. and lowest noise ratio
Option 3 will perform as option 2 ?
My application requires 1 balanced output, and one unbalanced output, also attached option for that
Thanks for all
Hi
What is the MSL rating of HMC902LP3E and HMC903LP3E? I can't find the MSL rating in the datasheets, and the parts do not have Material Declaration documents on the website.
Hello Tarang Jindal,
1) Trace interface has 1 clock and 16 data lines, but in pin muxing - lower 8 data lines and clock pins are repeated. so, please let us know,
---> Why lower 8 TRACE[0:7]_DATA and TRACE0_CLK are provided twice in pin mux.
---> is it possible to use only 1 TRACE clock with lower 8 TRACE[0:7]_DATA lines to support TRACE feature? which trace pod and connector will support this scenerio?
---> What is the difference in using 16 TRACE[0:15]_DATA vs using 8 TRACE[0:7]_DATA lines? What features we may loose by using the 8-trace lines
>> The total number of data lines relates to the throughput of the interface.
2) I have serached for the ADI emulator to support TRACE interface but not found any on ADI site. As per SC589 EVM user manual it is written that TRACE Pod are not yet available with ADI. so please let us know,
---> when will ADI provide TRACE pod to support ADSP-SC587 TRACE feature?
---> will the ADI TRACE pod support both "8-TRACE[7:0]_DATA + TRACE[0]_CLK" and "16-TRACE[15:0]_DATA- + TRACE[0]_CLK configutration
>> We do not have support for trace port yet.
Best Regards,
Jithul
Hi Vinod,
Thanks.For better understanding, I have attached our channel table which is starting from 4.4GHz to 5GHz. There are totally 6000 channels, We need to hop our radio between these channels.Our rate of hopping between these channels is 1000 hops/sec.. It means that the radio will change the transmission channel for every 1ms.
Note:
In the previous conversations, you used the term “maximum frequency change”. Does this mean the frequency difference between the current channel and the next switching channel (OR) the rate of frequency hopping (1000 hops/sec in our case). My understanding is first one. Please correct me if I am wrong.
Here is the two use cases ,
Case 1:
Let us assume that our radio is hopping from f1 (4400 MHz) to f3 (4400.2 MHz).
Q1:
Does this hopping require PLL lock + VCO Cal ?
Q2:
Does this hopping really require QEC?
Q3:
What is the minimum setting time required for this hopping?
Case 2:
Let us assume, in this case, our radio is hopping from f1 (4400 MHz) to f6000 (5000 MHz).
Q1:
Does this hopping require PLL lock + VCO Cal ?
Q2:
Does this hopping require QEC? If no, when it is need to be implemented.
Q3:
What is the minimum setting time required for this hopping?
Q4:
Does frequency separation matter when hopping?
Do let us know...
Thanks,
Muthu
Hi David
I configure the FPGA another once and increase the clock frequency to 100MHz.But I did't solve the problem.What can I do next？Thank you!
Hi Sir,
As title ,
Where Can i Find the software to control LTC5566 and set the SPI ,
Thanks for your help.
I am working with the ADXL362 but cannot get readings on the MISO line. The sensor is being powered by 2 V supply since the data sheet mentions it can work in the ranges of 1.65-3.5V. The clock, MOSI and CS look fine but the MISO line never changes and seems to have small spikes. I have also added 22 ohms resistors along the wire connections.
Any kind of help or suggestions would be appreciated!
Thanks!
Hi Zack,
i took a look at "C:\Program Files (x86)\LTC" but unfortunately, the directory does not exist!
I only have a folder created in "C:\Program Files\LTC\QuikEval" and there is only one .exe file to lunch.
Maybe the way the boards are recognized has changed with newer versions form the Quick Eval Software?
Its not so much important to our application, bit would be a nice future to check functionality on faulty boards....
Regards Danie
Hello
Thanks for the reply, but I think the LT8364 might be a better choice, due to it's higher current current capability at lower Vin.
Even that has <2A of capabilty at low Vin, but I am not sure I need quite 2A, and maybe they are conservative in their specs and might be basing that on a minimum efficiency.
Thanks for your question. It looks like the ADXL362 is not responding to your master. Do you power both VDDIO and VS at 2 V? Do your SPI master and slave run at different voltage level? Maybe you can also share your scope signal capture and schematic to check if everything is connected correctly and if SPI timing is OK.
Hi,
You can use the IDD specification:
Thank you very much.
Dear Jithul
Thanks for the reply,actually i need to calculate the checksum of our application code, here the checksum is for verification purpose to test every time the code is booted correctly or not, as specified we are calculating the XOR checksum, here i am not able to find from which address the checksum has to be calculated,since iam booting my application code from External flash,whether i have to take external flash address for calculating checksum or SRAM address?
If i need to take external flash address is it i have to take from 0x20000000(starting address of External flash)?
of if i have to take SRAM address can u specify address range(start and end address).
Best regards
Amar TR
Software engineer
SLN technologies.
I did not know SSM2142, because I never looked for an IC to balance an audio signal.
It 'a nice device but it needs and could not be otherwise, dual-type power supply.
This involves a more complex power supply and in any case the introduction of noise.
It always depends on what you want to get.
Surely the solution of the translator is more expensive and in my humble opinion, however, is the one that guarantees the best results.
Piero.
I use the AD9914 chip to generate two same DRG signals of 1.3G~1.4GHZ with the 3.5GHz reference clock being directly input. But there is jitter in the initial phase of the two LFM signals, wether is it becasue what you pointed out above? If YES, is it that mean as long as the system clock is 3.5GHz(upper than 2.5GHz), then my problem can not be solved?