Hi bem,
A rule of thumb in driving CMOS load: Ensure that an input representing a logic "low" is significantly lower than the input low level (VIL) and an input representing a logic "high" is significantly higher than the input high level (VIH). For this case, MCLK OUT of one device is the input to the MCLK IN pin of the other device. You can find the specs for the logic levels of MCLK OUT and MCLK IN on page 6 of the datasheet. VOL and VOH of MCLK OUT are comparatively higher than VIL and VIH of the MCLK IN. So, as long as 1 CMOS load is driving the MCLK OUT, cascading the clock from one device to another is possible.
However, the drawback I see for this setup is that if one device breaks or fails along the cascade, all of the devices that follow will suffer. I recommend a CMOS buffer is applied to the MCLK OUT signal from the first AD7705 before being applied to other MCLK IN pins.
Regards,
Johnny