Hi,
We don't have additional documentation other than the source code itself. The l_clk is generated from the rx_clk_in ports (using IBUFDS and BUFG modules).
The delay between the input and output is influence by the I/Q correction module (on TX path) and data format / dc filter / IQ correction modules (on the RX path). You could disable them by recompiling the design with DP_DISABLE set to 1.
We best support AD9361/AD9364 through our reference designs. If possible, use those for getting familiar with the IP and chip.
Regards,
Adrian