tDDDV is adjustable in register 0x006.
These control bits affect the DATA_CLK and the Rx data delays. The typical delay is approximately 0.3 ns/LSB. Rx Frame is delayed the same amount as the data port bits. Minimum delay setting is 0x0 and maximum delay is 0xF. Set this register so that the data from the AD9361 meets BBP setup/hold specifications.