Hi Istvan,
no it is not problem. I am just starting with zynq so a lot of things I should learn.
I checked reset and clocks and I am still not getting anything at output, also fifo_rd_valid
is always on zero. I checked all other signals and now I am really confused . All other
settings are set as Lars said. Do you have any other advice, only thing I can do is to
post you new complete design again.
Kind Regards,