Register programming is via the Serial Port Interface (SPI) port, which consists of 4 pins: CS, SCLK, SDO, SDIO. At power up, the device registers default to a state such that the SPI port is configured for 3-pin operation (i.e., SDO is not used and SDIO is bidirectional), which is probably what you want for your application.
The AD9910 Eval. Bd. provides a header and some jumpers that give you access to the SPI pins. I am by no means the "Eval. Bd. Expert", so perhaps someone else in the community can provide better detail on how to gain external access of the SPI port in regard to the Eval. Bd.
In any case, you need to control all three pins (CS, SCLK, SDIO) to access the registers. The CS pin serves as a gate signal (active low) telling the SPI port that you're ready to perform a serial communication. The SCLK pin is for a serial clock signal that you would provide for clocking data into the SDIO pin (write) or out of the SDIO pin (read). You'll need to follow the data sheet instructions on how to perform serial reads/writes. Basically, the first part of a serial sequence on the SDIO pin involves an instruction word, which tells the device whether you're reading or writing and also provides the address of the target register. The rest of the serial sequence is the data you are writing (in the case of a write sequence) or reading (in the case of a read sequence).
In the case of writing, once you've written data to all the registers you are interested in, you need to follow up with an IO_UPDATE. That is, you need to toggle the IO_UPDATE pin to get the device to transfer the SPI register contents to the internal buffer registers (which actually apply the data to the various circuit blocks within the device).
As a reminder, once you've programmed the registers (and assuming that programming included enabling the parallel data port), then once you toggle the IO_UPDATE pin the device starts latching in parallel data with each PDCLK cycle. Be aware, however, that TxEnable (which is like a 19th parallel data bit) determines how the device processes the 18b parallel data. If TxEnable is "true", the device uses the 18b data. If TxEnable is "false", the device ignores the 18b data and either substitutes "zero data" or retains the last word before TxEnable went "false" (depending on how you set CFR2[6]).
Hope this is sufficiently clear.