Hello rejeesh,
Thanks a lot for your reply. Appreciate your help.
In fact, I had the trouble with Zedboard FPGA banks based on the FMC interposer when I was trying to follow two references:
1) AD9279 Evaluation Board, ADC-FMC Interposer & Xilinx ML605 Reference Design [Analog Devices Wiki]
2) AD9467 Native FMC Card / Xilinx Reference Design [Analog Devices Wiki]
Currently, I modified BUFIO bank setup and it could compile. However, I don't know how to easily test my FPGA clock and sample data. I am not sure if my changes are meaningful at this stage. Would you like to instruct some solutions if we stop the FMC interposer route and make our own setup? The HSC-ADC-EVALCZ is not compact for us.
Thank you.
Linda