Hi Murali,
Checked your settings.
CVBS input changed to AIN11 with INSEL - OK.
You have the SFL pin pulled low in your schematic - best to disable this functionality - Reg 0x04[1] = 1'b0.
you are also measureing 28.5 MHz for your pixel clock - this should be 27MHz (+/- 5% depending on input source quality) - are you sure your not probing XTAL input here?
Can you try to bypass the differential to single ended converter and go single ended CVBS into AIN11 to see if this works?
regds,
Denis