Hi Michael,
Thanks for your initial update.
I have looked at all the references you have provided and you have answered a couple of things, however I still have some unanswered questions which I would like further understanding without having to reverse engineer the driver code.The main question is regarding your comment above:
"One leaves the decision to the SW how filters are used. (ad9361_calculate_ rf_clock_chain())"
I would like to know 'how' the software decides to set up the clock/filter chain, so that I can understand whether this function is suitable for our needs.
1) Is this function designed so it optimizes signal performance through the chain?
This will then hopefully answer my previous questions:
2) "Does the ad9361_calculate_ rf_clock_chain function try to program the ADC & DAC clocks to the highest frequency possible? At what point should the function decide it needs to use half band filters? Are there any profile guides available (power, performance, etc.) ?"
3)"Can the ad9361_calculate_ rf_clock_chain function be given a preference how to configure the chain? Does is consider the bandwidth requirement? E.g. is HB1 enabled prior to HB2?"
If a phone call is easier then I'd be happy to take this offline.
Kind Regards,
Andy