Dear Sir/Madam,
For those who are interested i have included the AD9681 PN-9 parallel equations and PN-9 sequence.
signal pn9_cs : std_logic_vector(13 downto 0) := "11" & X"FE0";
signal pn9_ns : std_logic_vector(13 downto 0);
signal pn9_twos_complement : std_logic_vector(13 downto 0);
..
..
process (Clk)
begin
if rising_edge(Clk) then
if Rst = '1' then
pn9_cs <= "11" & X"FE0";
else
pn9_cs <= pn9_ns;
end if;
end if;
end process;
-- Next state equations
pn9_ns(0) <= pn9_cs(1) xor pn9_cs(4) xor pn9_cs(5);
pn9_ns(1) <= pn9_cs(2) xor pn9_cs(5) xor pn9_cs(6);
pn9_ns(2) <= pn9_cs(3) xor pn9_cs(6) xor pn9_cs(7);
pn9_ns(3) <= pn9_cs(4) xor pn9_cs(7) xor pn9_cs(8);
pn9_ns(4) <= pn9_cs(0) xor pn9_cs(8);
pn9_ns(5) <= pn9_cs(0) xor pn9_cs(1) xor pn9_cs(5);
pn9_ns(6) <= pn9_cs(1) xor pn9_cs(2) xor pn9_cs(6);
pn9_ns(7) <= pn9_cs(2) xor pn9_cs(3) xor pn9_cs(7);
pn9_ns(8) <= pn9_cs(3) xor pn9_cs(4) xor pn9_cs(8);
pn9_ns(9) <= pn9_cs(0) xor pn9_cs(4);
pn9_ns(10) <= pn9_cs(1) xor pn9_cs(5);
pn9_ns(11) <= pn9_cs(2) xor pn9_cs(6);
pn9_ns(12) <= pn9_cs(3) xor pn9_cs(7);
pn9_ns(13) <= pn9_cs(4) xor pn9_cs(8);
-- Offset binary to two complement
pn9_twos_complement <= not pn9_cs(13) & pn9_cs(12 downto 0);
pn9_parallel <= pn9_twos_complement & "00";
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Regards Grant